The present invention relates to a delay data setting circuit and method whereby a delay time for a timing rate pulse of a test clock for each pin of an IC (a semiconductor integrated circuit) is set in a timing generator of an IC tester.
IC testers have been used for testing ICs to reject defective ICs or to analyze the defects in ICs. Such an IC tester generates test pattern data from a pattern generator, based on clocks from a timing generator, derives a signal waveform from pattern data contained in the test pattern data, based on the clocks from the timing generator, and converts the signal waveform into a signal voltage of an ECL or TTL level, which is supplied to corresponding one of pins of an IC under test. A response signal voltage obtained at each pin of the IC in this instance is subjected to a logical decision by comparison with a corresponding reference voltage and the logic thus decided is subjected to a logical comparison with expected value pattern data contained in the above-mentioned test pattern data, based on a clock from the timing generator. Thus it is necessary to obtain various test clocks from the timing generator.
The test clock is usually generated, based on a timing rate pulse, and the delay times of circuit elements and transmission lines to the IC tester are not always the same for each pin of the IC under test; therefore, test clocks for respective pins are set so that they are delayed for times .tau..sub.1, .tau..sub.2, . . . behind the timing rate pulse, respectively.
Conventionally, the setting of delay times is performed by a method which sequentially writes pieces of delay time data for respective pins into a delay data memory while sequentially specifying addresses therefor.
FIG. 1 shows an example of a device which implements the conventional setting method mentioned above. In this case, the number of pins of an IC (not shown) for which the delay times are to be set is 32 (hereinafter identified by P1, P2, P3, . . . , P32) and the delay time data is 32-bit.
A tester processor 10 and a delay data setting circuit 20, which forms an interface of a timing generator, are interconnected via an 8-bit data bus 30, a clock line 31 and a control line 32, and the delay data setting circuit 20 includes latch circuits 21 and 22, a sequence control circuit 20C and a delay data memory 23. The latch circuit 21 is made up of, for example, two 8-bit latches, which fetch data from the data bus 30, based on interface clocks CK1 and CK2, respectively. The latch circuit 22 is made up of, for example, four 8-bit latches, which fetch data from the data bus 30, based on interface clocks CK3, CK4, CK5 and CK6, respectively. The sequence control circuit 20C responds to a test start signal TS from the tester processor 10 to generate, in synchronization with a tester clock TCK, the interface clocks CK1 through CK6 and a write enable signal WE in a predetermined sequential order at a predetermined timing. The delay data memory 23 is a memory in which delay time data of 32 bits can be written at each of 32=2.sup.5 addresses.
As shown in FIG. 2, the sequence control circuit 20C responds to the test start signal TS to generate the interface clocks CK1 and CK2 in this order, by which 8-bit address data A1 and A2 from the tester processor 10 are sequentially fetched into the latch circuit 21. Of a total of 16 output bits from the latch circuit 21, five predetermined bits are provided, as address data for the pin P1, to an address terminal ADR of the delay data memory 23. The other output bits from the latch circuit 21 are used for the generation of a control signal in the delay data setting circuit 20, but this is a matter of design and hence will not be described. Next, delay time data of a total of 32 bits, for the pin P1, is transferred by the interface clocks CK1, CK2, CK3 and CK4, as 8-bit pieces of data D1, D2, D3 and D4 from the tester processor 10 to the latch circuit 22. The 32-bit delay time data is supplied to a data input terminal Di of the delay data memory 23. The time Tx for the transfer of the address data Al and A2 and the delay time data D1 through D4 from the tester processor 10 to the delay data memory 23 will hereinafter be referred to as a data fetch period. After completion of the data fetch period Tx the 32-bit delay data for the pin P1 is written into the delay data memory 23 at the address corresponding to the pin P1, by the write enable signal WE which is applied from the sequence control circuit 20C to a write enable terminal WE of the delay data memory 23 at predetermined timing. The time for this write will hereinafter be referred to as a data write period Ty. After writing of the data for the pin P1 into the memory 23, the tester processor 10 sends out the address data Al and A2 and the delay time data D1 through D4 for the pin P2, which are fetched into the latch circuits 21 and 22 by the interface clocks CK1 and CK2 and CK3 through CK6, respectively, and the delay time data thus fetched is written by the write enable signal WE into the memory 23 at the address corresponding to the pin P2. Thereafter pieces of delay time data for the pins P3, . . . P32 are similarly written into the delay data memory 23 at the addresses corresponding thereto.
Though not shown, the pieces of delay time data for the pins P1, P2, P3, . . . , P32, thus written into the delay data memory 23, are read out therefrom at its data output terminal Do. Based on the delay time data, test clocks for the pins P1, P2, P3, . . . , P32 are generated.
However, the above-described conventional method sequentially writes the pieces of delay time data for respective pins into the delay data memory 23 while sequentially specifying the addresses therefor, and hence takes much time for setting the delay time. Letting the time for fetching the address data and the delay time data from the tester processor 10 into the latch circuits 21 and 22 for each pin, the time for writing the delay time data into the delay data memory 23 for each pin and the total number of pins for which the delay times are to be set are represented by Tx, Ty and N, respectively, a period of time, N(Tx+Ty), is needed for setting the delay times in the memory 23 for all the pins.